1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a lateral power MOSFET.
2. Description of Related Art
The development of single chip process for integrating power switches with control circuitry is a major trend in the field of power IC development. The LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs. The LDMOS process involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction.
A LDMOS process using a reduced surface electric field (RESURF) technique with a low thickness EPI or N-well can achieve a high voltage with low on-resistance.
In recent developments, many high-voltage LDMOS transistors have been proposed by Klas H. Eklund, in U.S. Pat. No. 4,811,075 entitled “High Voltage MOS Transistors”; by Vladimir Rumennik and Robert W. Busse, in U.S. Pat. No. 5,258,636 entitled “Narrow Radius Tips for High Voltage Semiconductor Devices with Interdigitated Source and Drain Electrodes”. However, the drawback of theses prior arts is that aforementioned LDMOS transistors have higher on-resistance. Therefore, high voltage and low on-resistance LDMOS transistors are proposed by Klas H. Eklind, in U.S. Pat. No. 5,313,082 entitled “High Voltage MOS Transistor with a Low On-Resistance”; by Gen Tada, Akio Kitamura, Masaru Saito, and Naoto Fujishima, in U.S. Pat. No. 6,525,390 B2 entitled “MIS Semiconductor Device with Low On Resistance and High Breakdown Voltage”; by Vladimir Rumennik, Donald R. Disney, and Janardhanan S. Ajit, in U.S. Pat. No. 6,570,219 B1 entitled “High-voltage Transistor with Multi-layer Conductor Region”; by Masaaki Noda, in U.S. Pat. No. 6,617,652 B2 entitled “High Breakdown Voltage Semiconductor Device”. Although a high voltage and low on-resistance LDMOS transistor can be manufactured, the complexity of the production processes increases the production cost and/or reduces the production yield. Another disadvantage of these proposed transistors is none-isolated source structure. The none-isolated transistor current could flow around the substrate. This may generate noise interference in the control circuit. Besides, the current of the LDMOS transistor can generate a ground bounce to disturb the control signals. In order to solve these problems, the present invention proposes a LDMOS structure to realize a high breakdown voltage, low on-resistance and isolated transistor for the monolithic integration.